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Write down the VERILOG code for a tri-state buffer and the testbench code to test it

Write down the VERILOG code for a tri-state buffer and the testbench code to test it
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Answer #1

// Verilog Test Bench for tri-state buffer

module tb();

reg r_in_x;

reg w_enable;

wire w_output_x;

initial begin

$display("----------------------\nTri-State Buffer\n----------------------\n");


$monitor("input_x = %b, enable = %b, output_x = %b", r_in_x, w_enable, w_output_x);

// Generation of stimulus

r_in_x = 0;w_enable= 0;

# 10 r_in_x = 0;# 10 r_in_x = 1;# 10 w_enable = 1; # 10 r_in_x = 1;# 10 r_in_x = 0; # 10 w_enable = 1;

End

// Tri-state buffer instantiation

tristate_buffer u_tristate_buffer

( .input_x (r_in_x),

.enable (w_enable),  

.output_x (w_output_x));


endmodule

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