Question

Does a combinational device have a timing specification?

What bound is a combinational delay on the delay from any invalid input toan invalid output?

A lenient combinational device will not tolerate transitions and invalid levels on irrelevant inputs.

How many 3-­?input gates are there?

Glitches or hazards can be removed by removing gates from minimal logic designs.

What logic function is computed by the mux in Figure 4?

Can a full adder be made with a ROM?

Is state just stored information? Yes

Can we use positive feedback to maintain storage indefinitely?

Can we use a mux to make a latch?

Answer 1

combinational device have a timing specification in terms of delay.

we can bound the timing specifications tPD (propagation delay) and tCD (contamination delay) of an acyclic circuit of combinational components by considering cumulative delays along each input-to-output path through the circuit.

The output of lenient combinational device remains valid despite changes in irrelevent inputs.

6 (OR,AND,NOR,NAND,XOR,XNOR)

Glitches or hazards can be removed by adding gates from minimal logic designs.

Can a full adder may be made with a ROM

state is stored information.

positive feedback can restore and maintain information indefinitely, if the power supply is avaialable.

No, MUX is combinational circuit and does not have memory.