Question

F)The TCNT register is receiving an 8 MHz clock, If you are using an output compare with interrupts to delay 5.8 ms, can this be done without multiple interrupts?

G) Consider a 12bit timer subsystem similar to the HCS12’s. Assume that it has a 1 MHz clock. What is the interval between timer overflows?

H)For the same timer system described earlier (12 bits), what value should be loaded into the output compare register to create a delay of 100 microseconds?

I) The following C statements are used to initialize the free running counter (TCNT) timer system.

TSCR1 = 0x80; // turn on timer system TSCR2 = 0x00; // divide E clock by 1, no precaller

If these statements are executed, what is the duration of one count in the TCNT register? Assume a 24 MHz Eclock.

Answer 1

1. If TCNT is a 16-bit register, then it can be loaded with any value from 0x0000 to 0xFFFF. Time period for 8 MHz clock is 0.125 us.
   So the count value = 5.8 / 0.125 = 5.8 x 8 x 1000000 = 46400000. This value is more than 0xFFFF (65536), so to get delay of 5.8 ms, multple interrupts are needed.
   
2. Timer is of 12-bit, so it can count from zero to 1111_1111_1111 i.e. upto 0xFFF or in decimal it is 4095. So number of counts = 4096. Thus interval between timer overflows is equal to 4096 /1000000 = 4.096 ms.
   
3. For 100 us delay, count value = (100 x 10^-6)/10^-6 = 100. Thus output compare value must be loaded with the value 100 (assuming TCNT starts from zero).
   
4. No prescalar has been used so timer will get clock frequency of 24 MHz. Thus duration is same as time period of the clock = 1/24 us = 41.66 ns.