Question

Answer True or False(10marks)

1) VHDL language is case sensitive. a) True b) False

2) Variables in VHDL represent local information and update immediately. a) True b) false.

3) The concurrent statement in VHDL, output depends on previous input. a) True b) False

4) The case statement is only used in sequential code. a) True b) False

5) In VHDL package std_logic_arith.all specifies signed and unsigned data types. a) True b) False

Answer 1

(1) FALSE  

  VHDL language is case insensitive upper case letters are equivalent to lower case letters.

(2) TRUE

Yes ,Variables in VHDL represent local information and update immediately.

(3) FALSE

In  concurrent statement , output does not depends on previous input. So the Given statement is false .

(4) FALSE

case statement can be used in concurrent code statement .

(5) TRUE

  std_logic_arith.all package is used to specifies signed and unsigned data types.