Question

In an unpipelined processor, instruction throughput is exactly one per cycle. A pipelined processor has amortized throughput of one instruction per cycle, but only if stalls can be avoided; in practice throughput is something less than 1 and depends on things like the quality of the compiler and memory access patterns. Given that pipelining actually decreases IPC, how can we justify the added complexity it forces on the design?

Answer 1

An instruction pipeline increases the performance of a processor by overlapping the processing of several different instructions. An instruction pipeline overlaps the process of the preceding stages for different instructions to achieve a much lower total completion time, on average, for a series of instructions.

Three sources of architectural problems may affect the throughput of an instruction pipeline :

1 - The fetching problem

2 - The bottleneck problem

3 - The issuing problem

So, due to these problems we have added the complexity to our citcuit but the pipelining actually decreases IPC, so we need to find the solution to these prblems and then only we can improve the IPC throughpoy.