Question

Answer in about one paragraph. In an unpipelined processor, instruction throughput is exactly one per cycle. A pipelined processor has amortized throughput of one instruction per cycle, but only if stalls can be avoided; in practice throughput is something less than 1 and depends on things like the quality of the compiler and memory access patterns. Given that pipelining actually decreases IPC, how can we justify the added complexity it forces on the design?

Answer 1

The design of the pipeline is complex because the focus is on completing instructions per unit of time. This doesn't mean that execution time will decrease. Multiple instructions start overlapping when execution starts. This also allows buffered flow for information forward or unbuffered flow for sending data from one stage to another stage of pipeline. This also increases the depth of the pipeline. As the depth of the pipeline increases, the IPC or instruction per cycle is decreased. Because some part of every instruction is completed in parallel with each pipeline stage.

Hence the design is complex but does help in decreasing the IPC.