Question

Assuming that a computer system has 64MBytes of main memory, 16Bytes of cache line and 64KBytes...

Assuming that a computer system has 64MBytes of main memory, 16Bytes of cache line and 64KBytes of cache size. A main memory address contains “A1E3”data in a particular memory cell. Transfer this data to the cache in direct mapping, associative mapping and 16-way set-associative mapping algorithms.

Homework Answers

Answer #1

Cache Line = 16B => Block Offset = log 16 = 4 bits.

Total # of block inside cache => 64KB /16 = 4K

Main memory = 64MB => 26 bits.

For Direct Mapping,

Index offset = log(#of blocks) = log 4k = 12 bits

Tag = 26 - 12 - 4 = 10 bits

Tag(10 bits) Index Offset (12 bits) Cache Offset (4 bits)

A1E3 => 000A1E3 => 0000000000 101000011110 0100

So Index offset => 101000011110 => 2590.

So A1E3 would be transferred to block # 2590 of cache.

Association Mapping: Here there is no restriction on the main memory block. It can be placed anywhere inside the cache.

Thus A1E3 can be placed in any one of 4k blocks.

16 way set associative:

Total # of set inside cache => 4K/16 = 256

So index offset = log 256 = 8

So tag bits = 26 - 8 - 4 = 14

Tag(14 bits) Index Offset (8) Block Offset (4)

A1E3 => 1010 0001 1110 0011

Here index bits = 00011110 => 30

So the memory block A1E3 belongs to set # 30 of cache.

If you have any questions comment down. Please don't simply downvote and leave. If you are satisfied with answer, please? upvote thanks....

Know the answer?
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for?
Ask your own homework help question
Similar Questions
Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a...
Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a cache of 128 blocks, where each cache block contains 8 bytes. For four-way set associative cache, to which block of cache the address 0x1895BA maps? Group of answer choices Block 70 Block 16 Block 23 Not enough information
A 16 GB main memory has a 8 MB cache organized as a 8-way set associative...
A 16 GB main memory has a 8 MB cache organized as a 8-way set associative cache with 128 Byte cache blocks (line). How many cache blocks are there in the cache? How many sets are there in the cache? (Show your computation.) Show how the 36-bit address generated by the CPU would be divided to map into the cache. (Indicate the sizes of the tag, line, etc.)
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 1) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 2) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
1.) Perform the following multiplication using Booth’s algorithm: (You will receive full credit only if you...
1.) Perform the following multiplication using Booth’s algorithm: (You will receive full credit only if you show all your work)      13 x -13 (a) 27/4 Using paper pencil approach and (b) simulate how a machine does this job 2.)Perform the following division as directed: (a) 27/4 using non-restoring division algorithm // we need 4 quotient bits. (b) Using Newton-Raphson algorithm find 1/d when d=0.84 // show the results of the first 3 iterations 3.) A real-time computer system has...
The processor needs to transfer a file of 32768 kilobytes from disk to main memory. The...
The processor needs to transfer a file of 32768 kilobytes from disk to main memory. The memory is byte addressable. The size of the data count register of a DMA controller is 16 bits. What is the minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory in the following transfer modes 1.) Cycle stealing mode 2.) Burst Transfer mode
A computer system has 16 processing registers R0,···,R15, where each register has 32-bit storage capacity. The...
A computer system has 16 processing registers R0,···,R15, where each register has 32-bit storage capacity. The computer system uses a common bus system for data transfer between registers, memory and ALU. Answer the following questions if common bus is designed using multiplexers Size of each MUX needed for the design Number of MUXs needed Size of the bus (in bits)
Design a microcomputer system using a uP 8086 10MHz. This system must have a Coprocessor 8087,...
Design a microcomputer system using a uP 8086 10MHz. This system must have a Coprocessor 8087, a parallel connector, a serial connector, ADC and DAC connectors for data conversion, a 16 byte seven segment display, a 64-key matrix keyboard, a USB connector thru a DMA for high speed data transfer. A special connector to connect a printer. The system must have an interrupt controller. The main memory size will be 1Mbyte. Show all the diagrams needed to construct your design,...
Design a microcomputer system using a uP 8086 10MHz. This system must have a Coprocessor 8087,...
Design a microcomputer system using a uP 8086 10MHz. This system must have a Coprocessor 8087, a parallel connector, a serial connector, ADC and DAC connectors for data conversion, a 16 byte seven segment display, a 64-key matrix keyboard, a USB connector thru a DMA for high speed data transfer. A special connector to connect a printer. The system must have an interrupt controller. The main memory size will be 1Mbyte. Show all the diagrams needed to construct your design,...
1. The memory units that follow are specified by the number of words times the number...
1. The memory units that follow are specified by the number of words times the number of bits per word. How many address lines and input/output data lines are needed in each case? (a) 8K X 16 (b) 2G X 8 (c) 16M X 32 (d) 256K X 64 2. Give the number of bytes stored in each memory unit in question 1. 3. Word number 563 decimal in the memory shown in Fig. 7.3 (see Mano-Ch7.pdf) contains the binary...
ADVERTISEMENT
Need Online Homework Help?

Get Answers For Free
Most questions answered within 1 hours.

Ask a Question
ADVERTISEMENT