Question

A 16 GB main memory has a 8 MB cache organized as a 8-way set associative...

A 16 GB main memory has a 8 MB cache organized as a 8-way set associative cache with 128 Byte cache blocks (line). How many cache blocks are there in the cache? How many sets are there in the cache? (Show your computation.)

Show how the 36-bit address generated by the CPU would be divided to map into the cache.

(Indicate the sizes of the tag, line, etc.)

Homework Answers

Answer #1

number of blocks can be found with help of cache size and size of each block as shown here :

Number of sets :

Now, total memory is 16GB which is 2^34. so there is a mistake in question,

CUP generates memory address of 34 bits (assuming Byte Addressable).

Each address further gets divided into 3 parts. 1)tag bits 2) set bits 3) offset bits

In Cache, along with each block, tag bits for that block are stored too.

Following steps will be followed :

--> Find modulo :

lets say set bits of given address are : xxxx xxxx xxxx x

find modulo = (xxxx xxxx xxxx x) mod 213

result will give the set number of required block.

--> Compare tag bits of given address with tag bits of each of the 8 blocks stored in that set.

if the block is in cache, one block will have tab gits as same as the given address.

--> After finding block, add offsat bits to starting address of block. which will give required Byte from the block.

If you have any doubts, you can ask in comment section.

Know the answer?
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for?
Ask your own homework help question
Similar Questions
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 1) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 2) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
1. Suppose we have a 32KB direct-mapped data cache with 32-byte blocks. a) Show how a...
1. Suppose we have a 32KB direct-mapped data cache with 32-byte blocks. a) Show how a 32-bit memory address is divided into tag, index and offset. Show clearly how many bits are in each field. b) How many total bits are there in this cache? 2. Suppose we have a 8KB direct-mapped data cache with 64-byte blocks. a) Show how a 32-bit memory address is divided into tag, index and offset. Show clearly how many bits are in each field....
Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a...
Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a cache of 128 blocks, where each cache block contains 8 bytes. For four-way set associative cache, to which block of cache the address 0x1895BA maps? Group of answer choices Block 70 Block 16 Block 23 Not enough information
Consider a cache of 4 lines of 16 bytes each. Main memory is divided into blocks...
Consider a cache of 4 lines of 16 bytes each. Main memory is divided into blocks of 16 bytes each. That is, block 0 has bytes with addresses 0 through 15, and so on. Now consider a program that accesses memory in the following sequence of addresses: Once: 63 through 70. Loop two times: 15 through 32; 80 through 95. Suppose the cache is organized as two-​way set associative, with two sets of two lines each. Even-​numbered blocks are assigned...
1.) Perform the following multiplication using Booth’s algorithm: (You will receive full credit only if you...
1.) Perform the following multiplication using Booth’s algorithm: (You will receive full credit only if you show all your work)      13 x -13 (a) 27/4 Using paper pencil approach and (b) simulate how a machine does this job 2.)Perform the following division as directed: (a) 27/4 using non-restoring division algorithm // we need 4 quotient bits. (b) Using Newton-Raphson algorithm find 1/d when d=0.84 // show the results of the first 3 iterations 3.) A real-time computer system has...
1. The memory units that follow are specified by the number of words times the number...
1. The memory units that follow are specified by the number of words times the number of bits per word. How many address lines and input/output data lines are needed in each case? (a) 8K X 16 (b) 2G X 8 (c) 16M X 32 (d) 256K X 64 2. Give the number of bytes stored in each memory unit in question 1. 3. Word number 563 decimal in the memory shown in Fig. 7.3 (see Mano-Ch7.pdf) contains the binary...
Please answer the following Case analysis questions 1-How is New Balance performing compared to its primary...
Please answer the following Case analysis questions 1-How is New Balance performing compared to its primary rivals? How will the acquisition of Reebok by Adidas impact the structure of the athletic shoe industry? Is this likely to be favorable or unfavorable for New Balance? 2- What issues does New Balance management need to address? 3-What recommendations would you make to New Balance Management? What does New Balance need to do to continue to be successful? Should management continue to invest...