Question

The basic architecture diagram of CPU shows an adder with one input as the current instruction...

The basic architecture diagram of CPU shows an adder with one input as the current instruction address and the other with a fixed value of the number 4. What is the reason of this second input as 4?

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Due to the processor's pipeline nature and to guarantee that the program is consistent with codes, the reading value will be the instruction address plus 4 when the program counter is read during the execution of instructions. The word-aligned value of the instruction address plus 4 would be used if the program counter is used to generate addresses for memory accesses. This offset is continuous, regardless of how many instructions are combined. This guarantees consistency.

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