library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.ALL;
entity findmax is
port (
clk : in std_logic;
clr : in std_logic;
din : in real;
max : out real;
);
end findmax ;
architecture Behavioral of findmax is
signal m : real := 0.0;
begin
process begin
wait until rising_edge(clk);
if clr='1' then
m <= 0.0;
elsif din>m then
m <= din;
end if;
end if;
end process;
max <= m;
end Behavioral;
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