Question

entity one is
end;

architecture a of one is
  type arr is array(0 to 7) of bit_vector (2 downto 0);
  signal a : arr := ("000", "001", "010", "011", "100", "101", "110", "111");
  signal x : bit_vector (2 downto 0);
  signal y : bit;
  begin
    y <= x(0) and x(2); 
    process
      begin
         for i in 0 to 7 loop
            x <= a(i);
            wait for 1 ns;
            report bit'image(y);
          end loop;
        wait;
      end process;
end;

The output y is taken from the bit_vector x, and the bit_vector x is taken from one of the rows the (8x3) array a().

This module output y is a sequence 00000101000000101 where the bit times are 1 ns each. Modify this module (by changing just one line) to generate the sequence 0000001100000011. (In both cases the pattern period of 8-bits is the same.)

Answer 1

the code for the change in output is given below:

entity one is
end;

architecture a of one is
  type arr is array(0 to 7) of bit_vector (2 downto 0);
  signal a : arr := ("000", "001", "010", "011", "100", "101", "110", "111");
  signal x : bit_vector (2 downto 0);
  signal y : bit;
  begin
    y <= x(1) and x(2); -- x(0) is chnages to X(1) since we wantthe output 1 at 6-7 only hence 110 and 111 rest are 000 001 010 011(the first two bits wont give an output one for the change
    process
      begin
         for i in 0 to 7 loop
            x <= a(i);
            wait for 1 ns;
            report bit'image(y);
          end loop;
        wait;
      end process;
end;