Question

I am doing a howework assignment on structural verilog and was not sure how to answer these questions.

1) What is the file extension for a Xilinx Vivado constraint file?

2) In Verilog what is a signal called that comes from or goes to circuitry outside the defined module?

3) Describe the difference between the values “0”, “1”, “X”, and “Z”. Names for “X” and “Z” are worth zero points without a description of what they mean!

Answer 1

1) For vivado the constraint file is defined with an extension .xcf

2) The incoming signal to defined module is called as input port

   while the outgoing signals of defined module is called as output port

3) In verilog there are 4 values that a signal can take

   0 -- it is called logic Zero

   1 -- it is called logic One

   X or x -- it is callled Unkonwn logic

   An X bit might be a 0, 1, Z, or in transition. We can set bits to be X in situations where we don’t care what the value is. This can help catch bugs and improve synthesis quality.

Z or z -- it is called High impedance , floating