Question

The total addressable memory size is 64 KB for the Motorola 6800 microprocessor. Accumulator A (ACCA) is an 8-bit register used for arithmetic and logic operations.

Part A: - Explain the Instruction Set for the Motorola 6800 microprocessor. (cite your work)

- Explain the registers for the Motorola 6800 microprocessor. (cite your work)

Answer 1

Explain the Instruction Set for the Motorola 6800 microprocessor

Answer:-

For Motorola 6800, there are 72 different types of instructions and 197 different opcodes. So there are 51 one-Byte instruction, 103 two-Byte instruction and 43 three-Byte instruction. 6800 has advanced branching instructions as well.

The different instruction groups are like these −

• Data Transfer Group
• Arithmetic Group
• Logical Group
• Branch Group
• Miscellaneous Instructions

Data transfer Group

In this group, there are 14 instructions. We can find 38 opcodes for these 14 instructions. These instructions are like below.

Mnemonics	Number of Opcodes
LDA A/B, d8/a16/a8/IX+a8	8
STA A/B, a16/a8/IX+a8	6
LDS/LDX, d16/a16/a8/IX+a8	8
STS/STX a16/a8/IX+a8	6
PSH/PUL A/B	4
TAB/TBA/TSX/TXS/TAP/TPA	6

Arithmetic Group

In this group, there are 15 instructions. We can find 55 opcodes for these 15 instructions. These instructions are like below.

Mnemonics	Number of opcodes
ABA/SBA	2
SBC/SUB/ADC/ADD A/B d8/a8/a16/IX+ a8	32
INS/INX/DES/DEX	4
NEG/CLR/INC/DEC A/B/a16/IX + a8	16
DAA	1

Logical Group

In this group, there are 14 instructions. We can find 73 opcodes for these 14 instructions. These instructions are as below.

Mnemonics	Number of Opcodes
BIT/CMP/EOR/ORA/AND A/B, d8/a8/a16/IX + a8	40
ROR/ROL/LSR/ASR/ASL/COM/TSTA/B/a16/IX + a8	28
CPX d16/a8/a16/IX + a8	4
CBA	1

Here rotate instructions(ROR and ROL) are only for 8-bit data. The ASR and ASL are the arithmetic shift operations and LSR is Logical Shift Right instruction.

Branch Group

In this group, there are 21 instructions. We can find 23 opcodes for these 21 instructions.. Here the instruction for V flag is also present.These V related instructions are BVS (Branch when V flag is set), and BVC (Branch when V flag is reset). In 6800, the conditional branch instructions can check more than one flags. It helps to compare two signed/unsigned numbers. Here higher and lower keywords are used for unsigned numbers and greater and fewer keywords are used for signed numbers. So for these keywords, there are instructions like BHI(Branch if Higher), BLS(Branch if lower or same). The BGT(Branch if greater than) and BGE(Branch if greater and equal), BLT(Branch if Less than) and BLE(Branch if less than)

These instructions are like below.

Mnemonics	Number of Opcodes
BCC/BCS/BEQ/BNE/BMI/BPL/BVC/BVSr8	8
BHI/BLS r8	2
BGT/BGE/BLT/BLE r8	4
BRA/BSR r8	2
JMP/JSR a16/IX + a8	4
RTS/RTI	2
SWI	1

Miscellaneous Group

Now we will see some special instructions, which are not classified into some special groups. There are eight opcodes of eight different types. These instructions are like WAI(Wait for interrupt), NOP etc.

These instructions are like below.

Mnemonics	Number of Opcodes
WAI	1
NOP	1
CLC/SEC/CLI/SEI/CLV/SEV	6

Explain the registers for the Motorola 6800 microprocessor

Answer:-

The Motorola M6800 is 40pin DIP IC. It is an 8-bit Microprocessor. It was introduced in 1974 by Motorola. It was designed nearly at the same time when the 8080 was introduced. Like 8080, it also had 16-bit address bus to handle 64KB of data, and 8-bit data bus to read and write data.

The M6800 has very few registers. It has two Accumulators A and B, and the Index Register. This Microprocessor only supports the memory mapped IO because there is no instruction regarding IO operations in its instruction set.

The following are the Registers:-

Accumulator A (ACCA) is an 8-bit register used for arithmetic and logic operations.

Accumulator B (ACCB) is an 8-bit register used for arithmetic and logic operations.

Index (IX) is a 16-bit register usually used for temporary storage or as an index when indexed addressing is used.

Program counter (PC) is a 16-bit register.

Stack pointer (SP) is a 16-bit register.

Condition code register contains the following flags:

• Half carry (H) - set if there was a carry from bit 3 to bit 4 of the result when the result was calculated.
• Interrupt mask (I) - set if the IRQ interrupt is disabled.
• Negative (N) - set if the most significant bit of the result is set.
• Zero (Z) - set if the result is zero.
• Overflow (V) - set if there was an overflow during last result calculation.
• Carry (C) - set if there was a carry from the bit 7 during last result calculation