What would happen with the ring counter if the reset switch set the value of the counter to a ‘3’ instead of a ‘1’?
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There would be a false output, but the counter would continue to run in the proper order after the “3” state
The counter will count in the sequence: 3 -> 6 -> 5 -> 3 -> 6 -> ... which means two “on” outputs will be shifted left.
The “3” state was one that used don’t cares just like state “0” and it will be stuck there just like it was in state “0.”
It would be stuck in the “3” state and would not work properly.
The counter would go to a “6” state and then be stuck there.
The output would go in a random order until it hits one of the defined states. Once it hits a defined state, it will get back into the normal sequence.
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Question 2 1 pts
Without using asynchronous preset and clear inputs, what would need to be done to the design of the ring counter to assure that the first clock signal would set it into a valid state if it could be in any state when powered up?
Group of answer choices
Don’t use any don’t cares in the next state table. Specify what state (count) the counter will go to for each state the counter could start in.
Use a gated clock to control what state the counter starts at.
Use more flip flops so that the counter has more bits in it.
Add an RS latch to hold the D input stable.
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