Question

Can someone create a test bench for this code in VHDL. (Please type it out)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity USR_4Bit is

port( LR,SER,clk,clear,OC: in std_logic;

Da,Db,Dc,Dd: in std_logic;

Qa,Qb,Qc,Qd,QCas: out std_logic);

end USR_4Bit;

architecture Structural of USR_4Bit is

signal NLR,A1,A2,A3,A4,A5,A6,A7,A8: std_logic;

signal Nclear,Nclk,Q1,Q2,Q3,Q4:std_logic;

signal O1,O2,O3,O4 : std_logic;

component andgate

port(a,b: in std_logic; z : out std_logic);

end component;

component orgate

port(a,b: in std_logic; z : out std_logic);

end component;

component notgate

port(a: in std_logic; z : out std_logic);

end component;

component Dflipflop

port(D,clk,O: in std_logic; Q: out std_logic);

end component;

begin

NOTG1: notgate port map (LR,NLR);--1st notgate

NOTG2: notgate port map (clear,Nclear);--2nd notgate

NOTG3: notgate port map (clk,Nclk);--1st notgate

ANDG_1: andgate port map (Da,LR,A1); --1st bit

ANDG_2: andgate port map (SER,NLR,A2); --1st bit

ANDG_3: andgate port map (Db,LR,A3);--2st bit

ANDG_4: andgate port map (Q1,NLR,A4); -- 2nd bit

ANDG_5: andgate port map (Dc,LR,A5); --3nd bit

ANDG_6: andgate port map (Q2,NLR,A6);--3nd bit

ANDG_7: andgate port map (Dd,LR,A7); --4rd bit

ANDG_8: andgate port map (Q3,NLR,A8); --4rd bit

ORG1: orgate port map (A1,A2,O1);--for the 1st

ORG2: orgate port map (A3,A4,O2);--for the 2nd

ORG3: orgate port map (A5,A6,O3);--for the 3rd

ORG4: orgate port map (A7,A8,O4);--for the 4th

FF1: Dflipflop port map (O1,Nclear,Nclk,Q1);--FlipFlop = FF

FF2: Dflipflop port map (O2,Nclear,Nclk,Q2);

FF3: Dflipflop port map (O3,Nclear,Nclk,Q3);

FF4: Dflipflop port map (O4,Nclear,Nclk,Q4);

process(Q1,OC)

begin

    if OC ='1' then

        Qa<=not Q1;

    elsif (OC = '0') then

        Qa<=Q1;

    end if;

end process;

process(Q2,OC)

begin

    if OC ='1' then

        Qb<=not Q2;

    elsif (OC = '0') then

        Qb<=Q2;

    end if;

end process;

process(Q3,OC)

begin

    if OC ='1' then

        Qc<=not Q3;

    elsif (OC = '0') then

        Qc<=Q3;

    end if;

end process;

process(Q4,OC)

begin

    if OC ='1' then

        Qd<=not Q4;

    elsif (OC = '0') then

        Qd<=Q4;

    end if;

end process;

process(Q4)

begin

Qcas <= Q4;

end process;

end Structural;

Answer 1