Question

Write the VHDL code implementing a 6-bit synchronous counter with enable. The design should include the output to be connected to the next stage

Then update the code to include an asynchronous reset

Answer 1

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity vhdl_binary_counter is

port(enable, reset : in std_logic;

Q : out std_logic_vector(5 downto 0));

end vhdl_binary_counter;

architecture bhv of vhdl_binary_counter is

signal tmp: std_logic_vector(5 downto 0);

begin

process (enable, reset)

begin

if (reset=’1?) then

tmp <= "000000";

elsif (enable’event and enable=’1?) then

tmp <= tmp + 1;

end if;

end process;

Q <= tmp;

end bhv;