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7a) Design a timer circuit with an asynchronous set and reset and a clock input, and...

7a) Design a timer circuit with an asynchronous set and reset and a clock input, and a single output, such that the output is a logic 1 for 7 clock cycles, and then switches to a logic 0. The set input may be used to set the output to 1. Your circuit should include a counter.

b) Implement the above timer using behavioral Verilog.

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