Question

7a) Design a timer circuit with an asynchronous set and reset and a clock input, and a single output, such that the output is a logic 1 for 7 clock cycles, and then switches to a logic 0. The set input may be used to set the output to 1. Your circuit should include a counter.

b) Implement the above timer using behavioral Verilog.

Answer #1

Design a timer circuit with an asynchronous set and reset and a
clock input, and a single output, such that the output is a logic 1
for 7 clock cycles, and then switches to a logic 0. The set input
may be used to set the output to 1. Your circuit should include a
counter.

Counters and controllers
A circuit has two inputs a and b. A counter counts the number times
that in 3 consecutive clock pulses a and b are equal. Design this
circuit using a counter and basic logic gates and flip-flops. The
counting is modulo-16 and it rolls back to 0 after it reaches 15.
Provide an asynchronous reset input that resets the sequence
detection and the counting.

How do I design a divide by 4 clock in verilog using 2 D Flip
Flop blocks? I have created this divide by 2 clock D Flip Flop
block so far:
module divide_by_2(D, Clk,reset, Q, Qnext); //Divide by 2 clock
with reset using D flip flop
input Clk, D, reset;
output Q,Qnext;
reg Q;
assign Qnext = ~Q;
always @(posedge Clk or posedge reset) //always at the
positive edge of the clock or...

What would happen with the ring counter if the reset switch set
the value of the counter to a ‘3’ instead of a ‘1’?
Group of answer choices
There would be a false output, but the counter would continue to
run in the proper order after the “3” state
The counter will count in the sequence: 3 -> 6 -> 5 ->
3 -> 6 -> ... which means two “on” outputs will be shifted
left.
The “3” state was...

Design a counter which counts in the sequence that has
been assigned to you. Use D flip flops and NAND gates. Simulate
your design using SimUaid.
Submit the state table, D flip-flop input equations,
and transition graph determined in Part 6. The D flip-flop
equations can be derived using Karnaugh maps or using LogicAid by
entering a state table with zero input variables.
Sequence: 000,100,001,110,101,111,(repeat)
000,...
Also, please answer the following questions:
How can a D flip-flop be set to...

Using Moore machine approach design a sequence detector with one
input and one output. When input
sequence 010 occurs the output becomes 1 and remains 1 until the
sequence 010 occurs again in which case the
output returns to 0. The output remains 0 until, 010 occurs the
third time, and so on. Your design should be
able to handle overlapping sequences, i.e., input sequence
11001010100 should produce the output 00000110011.
Draw the state diagram and implement your detector using...

Implement the following circuit to test the characteristics of
a D flip flop.
Note:
Using a clock input to operate the flip-flop is rather
quickly.
You may wish to select the slow motion of the clock OR
to use a simple binary input device instead of a clock input
device.
Verify the flip flop state table.
Q(t+1) = D, is the characteristic equation.
Characteristic Table Excitation Table
==================== ===================
D Q(t+1) Operation Q(t) Q(t+1) D
==================== ===================
0 0 Reset...

Verilog HDL
Design a logic module to multiply an 8-bit binary number A [0:7]
by a 4-bit binary
number N [0:3]. The multiply is started when M is asserted. The
output F is asserted
when the multiply is completed and the product P [0: 15] is
available. The outputs need to
remain valid until the next multiply command is given. Assume M
is valid for several of
your clock cycles and then is de-asserted.
Implement the multiply using repeated addition...

Design a synchronous up/down 2-bit counter. The circuit has a
single input (X), when X=1, the counter counts up (i.e.
0,1,2,3,0,1.....), when X=0, the counter counts down (i.e.
3,2,1,0,3,2,....). Show work, including a next-state table and
circuit diagram.

Design a 6-bit, shift-right register with D flip flops, and use
it to implement a circuit that detects the sequence “010010” (the
rightmost bit is the first arriving). Information shifts one
position right when a positiv edge of clk occurs The circuit has
the following inputs and outputs (use exactly these names for
inputs and outputs. Respect upper and lower case):
clk: Input. Clock signal.
RST: Reset signal. When RST = 1 flip flops are reset to 0.
IN: Data...

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