Question

desgin sychonrous sequential circuit steps through 1,3,5,7,4,2,0,6 and repeat implement the circuit in verilog . drive the seven segment display

Answer 1

State Table

PRESENT STATE			NEXT STATE
Q2	Q1	Q0	Q2+	Q1+	Q0+
0	0	0	1	1	0
0	0	1	0	1	1
0	1	0	0	0	0
0	1	1	1	0	1
1	0	0	0	1	0
1	0	1	1	1	1
1	1	0	0	0	1
1	1	1	1	0	0

Circuit is implemented using D Flip Flop and Hence we derive excitation equation for the D flip flop inputs

Circuit

//Now behavioral model of circuit in verilog is shown below.

//Seven Segment display is assumed to be common cathode type

//Verilog Code

module synchronous_circuit (clock, reset, display);

input clock, reset;

output reg [6:0] display;

parameter S0=3'b000, S1=3'b001, S2=3'b010, S3=3'b011, S4=3'b100, S5=3'b101, S6=3'b110, S7=3'b111;

reg [2:0] current_state, next_state;

always @ (posedge clock)
begin
   if (reset)
       current_state <= S0;
   else
       current_state <= next_state;
end

always @(current_state)
begin
   case (current_state)
       S0:   next_state <= S6;
       S1:   next_state <= S3;
       S2:   next_state <= S0;
       S3:   next_state <= S5;
       S4:   next_state <= S2;
       S5:   next_state <= S7;
       S6:   next_state <= S1;
       S7:   next_state <= S4;
       default:next_state <= S0;
   endcase
end

always @(current_state)
begin
   case (current_state)
       S0:   display <= 7'b0000001; //abcdefg segments
       S1:   display <= 7'b1001111;
       S2:   display <= 7'b0010010;
       S3:   display <= 7'b0000110;
       S4:   display <= 7'b1001100;
       S5:   display <= 7'b0100100;
       S6:   display <= 7'b0100000;
       S7:   display <= 7'b0001111;
       default:display <= 7'b1111111;
   endcase
end

endmodule

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//Simulated on ModelSim