Using Moore machine approach design a sequence detector with one
input and one output. When input
sequence 010 occurs the output becomes 1 and remains 1 until the
sequence 010 occurs again in which case the
output returns to 0. The output remains 0 until, 010 occurs the
third time, and so on. Your design should be
able to handle overlapping sequences, i.e., input sequence
11001010100 should produce the output 00000110011.
Draw the state diagram and implement your detector using D
flip-flops and the combinatorial gates of your
choice. Show all work.
Implement the finite state machine behaviorally
using your design from prefab. Design a behavioral
test
circuitwhich generates the test sequence shown above:
”11001010100”.
Behavilrally code in verilog please.
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