Question

Q1)Design a 3-bit full adder by using a 8x3 Decoder.,

Q2)Design a digital circuit by using a 8x1 multiplexer implementing the following Boolean equation.F(A, B, C, D) =∑(2, 3, 5, 7, 8, 9, 12, 13, 14, 15)

Answer #1

Design a Single cell 1 bit Carry propagate (or Ripple Carry
Adder) full adder.
a. Generate the truth table
b. Using K-map or Boolean algebra, determine the logical
expression for Carry out (C-out) and Sum (S) Outputs
C. Draw the circuit diagram of the outputs in step b

Design a 1-bit Full adder using one 3-bit majority encoder and a
set of NAND gates

Design a circuit that computes F = 4.5A (4.5 times A) using a
full adder. Input A is a 4-bit number (A3A2A1A0) and A is an even
number. A3 is the MSB.

Design a 4-bit adder-subtractor circuit using the 4-bit binary
Full adders (74LS83) and any necessary additional logic gates. The
circuit has a mode input bit, M, that controls its operation.
Specifically, when M=0, the circuit becomes a 4-bit adder, and when
M=1, the circuit becomes a 4-bit subtractor that performs the
operation A plus the 2’s complement of B.Where A and B are two
4-bits binary numbers. That is,
* When M=0, we perform A+B, and we assume that
both...

Adder
Start out by picking 2 positive six bit binary numbers that are
less than 3210, written in 2's complement notation. The
eventual goal is to add these two numbers.
1) Look at the LSB bit of the numbers, and using logic gates
(NANDs, NORs, etc.) design a circuit that correctly gives the right
output for any possible combination of bits in the LSB place.
2) Now look at the next column to the left (next to LSB). In
this...

Using Quartus II and the DE2 board, design and demonstrate a
3-bit up-counter; use D flip flops for this project. Use one of the
debounce switches for a clock and 3 LEDs to indicate the count.
Implementing PRE and CLR will improve your design.
1. Please hand in a schematic and functional and timing
simulation of your circuit.

VIVA QUESTIONS: 1. Implement the following function using VHDL
coding. (Try to minimize if you can). F(A,B,C,D)=(A'+B+C).
(A+B'+D'). (B+C'+D') . (A+B+C+D) 2. What will be the no. of rows in
the truth table of N variables? 3. What are the advantages of VHDL?
4. Design Ex-OR gate using behavioral model? 5. Implement the
following function using VHDL code f=AB+CD. 6. What are the
differences between half adder and full adder? 7. What are the
advantages of minimizing the logical expressions?...

Year
Quarter
Sales
1
Q1
7
Q2
2
Q3
4
Q4
10
2
Q1
6
Q2
3
Q3
8
Q4
14
3
Q1
10
Q2
3
Q3
5
Q4
16
4
Q1
12
Q2
4
Q3
7
Q4
22
1.Develop a model for trend and seasonality. Please clearly
define your variables. How many independent variables do you have
in your regression?
2.What is the intercept in your estimated regression model?
Rounded to two decimal places.
3.Use the model to forecast...

by MULTISIM Design a 4 bit Counter that
displays even numbers when a switch on, and odd
when the switch off .
i want you to desgin that cirucit in MULTIsim by useing Jk flip
flop please make it easy to understand and memories =[
that mean if it was even= 0 its will count 0 , 2 , 4 ,6 , 8 , 10
, 14
if it is odd = 1 its will count 1 , 3 ,...

Using T-Flip-flops, design a 3-bit register/counter circuit with
bits [A2 A1 A0]. The circuit operations are described in the
following table. Show all design details, i.e., write down steps
and equations and draw the detailed circuit diagram. S2 S1 S0
Operation 0 0 0 No change 0 0 1 Rotate left 0 1 0 Rotate right 0 1
1 Reset 1 0 0 Set 1 0 1 Count down 1 1 0 Count up 1 1 1 Load
external bits...

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