Question

Verilog HDL

Design a logic module to multiply an 8-bit binary number A [0:7] by a 4-bit binary

number N [0:3]. The multiply is started when M is asserted. The output F is asserted

when the multiply is completed and the product P [0: 15] is available. The outputs need to

remain valid until the next multiply command is given. Assume M is valid for several of

your clock cycles and then is de-asserted.

Implement the multiply using repeated addition of A to form partial products

Answer 1

module multiplier (clk,A, N, M, F, P);

input clk;

input [0:7] A;

input [0:3] N;

input M;

output reg F;

output reg [0:15] P;

reg [0:3] Mplier;

reg [0:15] Product;

always @ (posedge M) begin

Mplier <= N;

Product = 16'b0000000000000000;

end

always @ (posedge clk) begin

if (M == 1) begin

if ( Mplier != 0) begin

Mplier = Mplier - 1;

Product = Product + A;

F = 0;

end

else begin

F = 1;

P = Product;

end

end

end

endmodule