Question

Using three rising-edge-triggered T flip-flops and a minumum
number of additional gates, construct a circuit that will operate
as a binary counter with an enable signal *E*. When
*E* = 1, the counter should increment from 0 to 7 on each
clock pulse, with (flip-flop outputs
*Q**2**Q**1**Q**0* = 000-
001-010-011-100-101-110-111) and then roll over to 000 and repeat
the sequence. When *E*=0, the counter should stop and hold
its current count.

Note: (not modulo-8, but modulo-6: 000-001-010-011-100-101-000- ... )

Answer #1

We wish to design a digital system with two
flip-flops, say B and C, and one 10 bit binary Counter A, in which
the individual flip-flops are denoted by A10, A9, A8, A7, A6, A5,
A4, A3, A2, A1.
A start signal S initiates the system operation by clearing the
counter A and flip-flop C, and setting flip-flop B to one.
The counter is then incremented by one starting from the next
clock pulse and continues to increment until the...

Design a 6-bit, shift-right register with D flip flops, and use
it to implement a circuit that detects the sequence “010010” (the
rightmost bit is the first arriving). Information shifts one
position right when a positiv edge of clk occurs The circuit has
the following inputs and outputs (use exactly these names for
inputs and outputs. Respect upper and lower case):
clk: Input. Clock signal.
RST: Reset signal. When RST = 1 flip flops are reset to 0.
IN: Data...

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