Question

A 128K X 32 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select. (a) Assuming that the RAM cell array is square, what is the size of each decoder? (b) Determine the row and column selection lines that are enabled when the input address is 0x39ABCD. (c) Why is "squareness" a good assumption?

Answer 1

Row decoder has size 8 -to- 2^8 = 256 Column decoder has size 7 -to- 2^7 = 128 If coincident decoding had not been used, the single decoder would have had 15 inputs and 2^15 = 32768 outputs. Determine in decimal the row and column selection lines that are enabled when the input address is the binary equivalent of (11133) 10 : Row selection line = 86 Column selection line = 125 You received a raw score of 100% on this question. WebQuiz Grade Summary Raw score 100.00% Adjusted score 100.00% Minimum passing score 60.00% Grade for this submission 100% Cumulative Grade 100% Mallard ECE 290: Computer Engineering I - Spring 2007 - Graded Web.