Question

12.4.1 - How long is a PWM signal HIGH for if the period is 500ms and...

12.4.1 - How long is a PWM signal HIGH for if the period is 500ms and the duty cycle is 10%?

Question 1 options:

500 ms

0 s

50 ms

450 ms

12.4.2 - How long is a PWM signal LOW for if the period is 500ms and the duty cycle is 10%?

Question 2 options:

500 ms

0 s

50 ms

450 ms

12.4.5 - You are going to generate a PWM signal with a period of 700ms and a duty cycle of 10%. You are using ACLK with no dividers as the timer clock with the timer running in 16-bit up mode. What value should you put into CCR0 to set the PWM period?

Question 3 options:

10

22,938

200

2,294
Engineering   Electrical-Engineering   
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