Question

Please write the testbench of T-flip flop in VHDL with using assert or wait function. thank you.

Here my Tff code:

module Tff (e,clk,re,q);

input e,clk,re;

ouput q;

always_ff@(posedge clk) begin

if (re) q=0;

else q<=q+1;

end

endmodule

Answer 1

module Tff (T,clk,re,q);

input T,clk,re;

output reg q;

always_ff @(posedge clk) begin

if (re) q <= 0;

else if (T) q<=q+1;

end

endmodule

module TFF_tb;

reg clk, re;

reg T;

wire q;

integer i;

Tff DUT (.clk(clk), .re(re), .T(T), .q(q));

always

#5 clk = ~clk;

initial

begin

clk = 1'b0;

re = 1'b1;

T = 1'b0;

repeat(2)

@(negedge clk);

re = 1'b0;

for (i = 0; i < 10; i = i + 1)

begin

T = 1'b0; @(negedge clk);

T = 1'b1; @(negedge clk);

T = 1'b0; @(negedge clk);

end

$finish;

end

initial begin // dump creation for waveform

$dumpfile("dump.vcd");

$dumpvars;

end

endmodule