Question

**Design a counter which counts in the sequence that has
been assigned to you. Use D flip flops and NAND gates. Simulate
your design using** **SimUaid.**

**Submit the state table, D flip-flop input equations,
and transition graph determined in Part 6. The D flip-flop
equations can be derived using Karnaugh maps or using LogicAid by
entering a state table with zero input variables.**

**Sequence: 000,100,001,110,101,111,(repeat)
000,...**

Also, please answer the following questions:

How can a D flip-flop be set to logic 0 without using the clock input?

How can it be set to logic 1 without using the clock input?

Explain the term *Asynchronous Input*.

Design a counter that counts in the sequence assigned to you.
Use D flip-flops, NAND gates, and inverters. Draw your circuit
explicitly showing all connections to gate and flip-flop inputs.
**Explicitly means that you should draw in all wires, don’t
just label the inputs and outputs. Show switches connected to the
Preset and Clear inputs of the flip-flops. Use
one switch for all clears and a separate switch for each
preset.**

Explain in detail how you can set the flip-flops to the two missing states not in the prescribed counting sequence without using the clock input. Your explanation should describe each change you make to a switch position. After you have cleared or set a flip-flop, in what position (0 or 1) should you leave the switches?

Answer #1

Sequence is 000,0110,111,100,101,001,
(repeat)000,…· Design a counter that counts in the sequence assigned to you.
Use D flip-flops, NAND gates, and inverters. Draw your circuit
explicitly showing all connections to gate and flip-flop inputs.Explicitly means that you should draw in all wires, don’t
just label the inputs and outputs. Show switches connected to thePreset and Clear inputs of the flip-flops. Use
one switch for all clears and a separate switch for each
preset.· Explain in detail how you can set...

Counters and controllers
A circuit has two inputs a and b. A counter counts the number times
that in 3 consecutive clock pulses a and b are equal. Design this
circuit using a counter and basic logic gates and flip-flops. The
counting is modulo-16 and it rolls back to 0 after it reaches 15.
Provide an asynchronous reset input that resets the sequence
detection and the counting.

Ripple Counters and T-FFs.
(a) Design a 5-bit ripple down-counter using T Flip-Flops and no
other components.
(b) Design a 5-bit ripple up-counter using T Flip-Flops and no
other components.
(c) What limits the maximum counting speed of your ripple
counters?
(d) Design a T Flip-Flop using only a D flip-flop with no extra
logic gates.

6. Please design a self-start 2-bit counter using the Finite
State machine. Note you can formulate the State truth table
(Present State/Next State/Inputs). Please design it using D
Flip-Flops or T-Flip Flops and combination gates. Current State
Next State input Q1Q0 Q1’Q0’ D1D0 (T1T0) 00 01 01 10

Use JK Flip Flop to design a 2-bit synchronous counter (up
counter) that counts down as given: AB = 01, 11, 00, 10, and then
again 01. Show the design steps (e.g state table, j and k inputs
for k-maps etc) and draw the final circuit.

Using Quartus II and the DE2 board, design and demonstrate a
3-bit up-counter; use D flip flops for this project. Use one of the
debounce switches for a clock and 3 LEDs to indicate the count.
Implementing PRE and CLR will improve your design.
1. Please hand in a schematic and functional and timing
simulation of your circuit.

Design a 6-bit, shift-right register with D flip flops, and use
it to implement a circuit that detects the sequence “010010” (the
rightmost bit is the first arriving). Information shifts one
position right when a positiv edge of clk occurs The circuit has
the following inputs and outputs (use exactly these names for
inputs and outputs. Respect upper and lower case):
clk: Input. Clock signal.
RST: Reset signal. When RST = 1 flip flops are reset to 0.
IN: Data...

Design a synchronous machine (Transition Table, K-maps, Final
Equations, Circuit Diagram) that counts through the following
sequence in the order shown below. Note, there are no inputs or
output variables, so your Q values must reflect the Hex value
listed.
A 4 1 2 6 3 9 C 7 and repeat
a) using D flip-flops and combinational logic
b) using a PROM device (must show Hex values in order) and 4-bit
D-Register

Design a sequencer using J-K flip-flops that will sequence
through the following states and then repeat the sequence in
response to successive clock pulses:
0,1,3,5,7,4,0,…………..
PLEASE INCLUDE ALL OF THE FOLLOWING:
-a state diagram
-a binary state transition table
-K-maps and reduced expressions for all J-K inputs
-logic diagram

Show a complete design of a Mealy detector that detects the
sequence 11001 on its j input. The output of the circuit
is w. Show the complete gate-level design using basic
gates and D flip-flops.

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