Question

Design and code a Verilog module to convert a 4 digit unsigned BCD whole number into...

Design and code a Verilog module to convert a 4 digit unsigned BCD whole number into a 14 bit binary number.

Homework Answers

Answer #1
module bcd2bin_direct
   (
    input wire [3:0] bcd3, bcd2, bcd1, bcd0,
    output wire [13:0] bin
   );
   wire [13:0] thousand;
   wire [9:0]  hundred;
   wire [6:0]  ten;

   // thousand  = 512 + 256 + 128 + 64 + 32 + 8
   assign thousand = (bcd3 << 9) + (bcd3 << 8)+ (bcd3 << 7) + (bcd3 << 6) + (bcd3 << 5) + (bcd3 << 3);
   
  // hundred = 64 + 32 + 4
   assign hundred = (bcd2 << 6) + (bcd2 << 5) + (bcd2 << 4);

   // ten  = 8 + 2
   assign ten = (bcd1 << 3) + (bcd1 << 1);

   assign bin = thousand + hundred + ten + bcd0;

endmodule
Know the answer?
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for?
Ask your own homework help question
Similar Questions
Design a module that can perform a binary-coded decimal (BCD) addition. You have two 4-bit BCD...
Design a module that can perform a binary-coded decimal (BCD) addition. You have two 4-bit BCD (decimal digits 0 to 9) inputs “a” and “b” and an 8-bit output “x” which represents a two digit BCD number. X [7:4] represents the upper BCD digits X [3:0] represents the lower BCD digits In the Verilog file, please code a BCD adder. It should follow the following format. module bcd_adder( a,b,x ); input wire [3:0] a; input wire [3:0] b; output reg...
Design a module using Verilog’s behavioral design method that can perform a BCD to seven segment...
Design a module using Verilog’s behavioral design method that can perform a BCD to seven segment display decoder. This module receives a 4-bit binary input and generates the seven output signals (a - g) plus DP (dot pixel) for the display. module bcd_to_seven( bin_in, sseg_out); input wire [3:0] bin_in; output reg [7:0] sseg_out; endmodule The inputs bin_in should be binary 0 to 15. The outputs of sseg_out should drive a seven segment display to indicate a number from 0 -...
Verilog HDL Design a logic module to multiply an 8-bit binary number A [0:7] by a...
Verilog HDL Design a logic module to multiply an 8-bit binary number A [0:7] by a 4-bit binary number N [0:3]. The multiply is started when M is asserted. The output F is asserted when the multiply is completed and the product P [0: 15] is available. The outputs need to remain valid until the next multiply command is given. Assume M is valid for several of your clock cycles and then is de-asserted. Implement the multiply using repeated addition...
1-What is the decimal number of the binary numbers (101111)2? 2-What is 123 in BCD code?...
1-What is the decimal number of the binary numbers (101111)2? 2-What is 123 in BCD code? 3-Convert the binary (10101011101)2 into octal and hexadecimal? 4-What is 2's complement of (1101110)2? 5-Convert the decimal number 152.25 into binary?
Design a verilog code for four-bit subtractor. write the simulation code and constraints file for nexys...
Design a verilog code for four-bit subtractor. write the simulation code and constraints file for nexys 4.
Design a two bit Gray to binary code converter.      Convert the SOP form into POS for...
Design a two bit Gray to binary code converter.      Convert the SOP form into POS for the expression- AB’C+AB +A’BC
convert this number into BCD code ( 47 to 01000111) you will have 8 bits data...
convert this number into BCD code ( 47 to 01000111) you will have 8 bits data d(t) = 01000111 sketch the timeing and state diagrams of the following signals: 1) PSK 2) DPSK 3) BPSK 4) OPSK 5) pi/4- QPSK 6) MSK
Design a 4 to 16 decoder using Verilog HDL. The inputs are a four-bit vector W=...
Design a 4 to 16 decoder using Verilog HDL. The inputs are a four-bit vector W= [w1 w2 w3 w4] and an enable signal En. The outputs are represented by the 16-bit vector Y= [y0 y1 …..y15]. a) Write Verilog HDL behavioral style code for 2-to-4 decoder. b) Write Verilog HDL behavioral style code for 4-to-16 decoder by instantiation of 2-to-4 decoders.
Design a 4 to 16 decoder using Verilog HDL. The inputs are a four-bit vector W=...
Design a 4 to 16 decoder using Verilog HDL. The inputs are a four-bit vector W= [w1 w2 w3 w4] and an enable signal En. The outputs are represented by the 16-bit vector Y= [y0 y1 …..y15]. a) Write Verilog HDL behavioral style code for 2-to-4 decoder. b) Write Verilog HDL behavioral style code for 4-to-16 decoder by instantiation of 2-to-4 decoders.
(ii) Create a hierarchical Verilog 5-to-1 mux module with five data inputs (a, b, c, d,...
(ii) Create a hierarchical Verilog 5-to-1 mux module with five data inputs (a, b, c, d, e), three select inputs (s[2:0]), and one output bit (f) using 4-to-1 multiplexers. Design the 4-to-1 multiplexer using behavioral code.
ADVERTISEMENT
Need Online Homework Help?

Get Answers For Free
Most questions answered within 1 hours.

Ask a Question
ADVERTISEMENT