Question

Design a resistively loaded NMOS inverter to operate from a 3.3-V power supply. The inverter should dissipate not more than P = 0.2 mW. The low voltage input (‘low logic input’) is VL = 0.2 V. Assume VTN = 0.7 V. Also the transconductance value is Kn = 100x10-6 A/V2 . Assumptions: (a) the transistor is ‘off’ when VI = VL and (b) the transistor is the triode region for VO = VL.

Answer 1