Question

Use JK Flip Flop to design a 2-bit synchronous counter (up counter) that counts down as given: AB = 01, 11, 00, 10, and then again 01. Show the design steps (e.g state table, j and k inputs for k-maps etc) and draw the final circuit.

Answer #1

In case you have any doubts or you did not understand any step please feel free to ask your doubts in the comments section. I would be happy to clarify it.

**DO GIVE A THUMBS UP !!**

Design a 2-bit binary counter using one JK and one T flip flop.
Derive the equations for JA, KA and TB. Do not draw the
circuit.

can
someone do 3 bit counter USING a SR, JK, and D flip flop. With a
pattern of 7,6,5,4,3,2,1. showing the steps w tables(present, next,
etc)

Design a synchronous up/down 2-bit counter. The circuit has a
single input (X), when X=1, the counter counts up (i.e.
0,1,2,3,0,1.....), when X=0, the counter counts down (i.e.
3,2,1,0,3,2,....). Show work, including a next-state table and
circuit diagram.

1.a) A counter is designed to go through the sequence :
1,3,5,7,0,2,5,6, repeat, Using JK flipflops: (i) Construct the
state table. (ii) Draw the circuit. b) A sequential circuit is
constructed with one T flip-flop A, one D flip-flop B and one input
X, when X=0, the state of the circuit remains the same. When X=1,
the circuit goes through the transitions from 00 to 01 to 11 to 10
back to 00, repeat. (i) Draw the state transition diagram...

Design a counter which counts in the sequence that has
been assigned to you. Use D flip flops and NAND gates. Simulate
your design using SimUaid.
Submit the state table, D flip-flop input equations,
and transition graph determined in Part 6. The D flip-flop
equations can be derived using Karnaugh maps or using LogicAid by
entering a state table with zero input variables.
Sequence: 000,100,001,110,101,111,(repeat)
000,...
Also, please answer the following questions:
How can a D flip-flop be set to...

Ripple Counters and T-FFs.
(a) Design a 5-bit ripple down-counter using T Flip-Flops and no
other components.
(b) Design a 5-bit ripple up-counter using T Flip-Flops and no
other components.
(c) What limits the maximum counting speed of your ripple
counters?
(d) Design a T Flip-Flop using only a D flip-flop with no extra
logic gates.

Design a synchronous machine (Transition Table, K-maps, Final
Equations, Circuit Diagram) that counts through the following
sequence in the order shown below. Note, there are no inputs or
output variables, so your Q values must reflect the Hex value
listed.
A 4 1 2 6 3 9 C 7 and repeat
a) using D flip-flops and combinational logic
b) using a PROM device (must show Hex values in order) and 4-bit
D-Register

Design a circuit for a synchronous 4-bit counter. Your counter
should count up starting from 0 to 9 (00002
to 10012)
and then wind back to 0 (00002)
–
after 9, it should go back to 0.
Use 4 JK flip-flops and any other gates you need. Include your
design documentation in your submission:
a.
Truth table
b.
Simplification (show your work)
2.
Build this circuit in
Logisim.
Please label each gate, including flip-flops. You may need the
following wiring...

Design the following state machine using JK flip-flops:
A state machine outputs a 1 when the sequence 010110 is
recognized and your design must accommodate overlaps. When the
sequence is detected, the sequence is detected, the sequence
detection must be signaled immediately when the last bit in the
sequence is input. Derive the K-maps for all excitation inputs.

6. Please design a self-start 2-bit counter using the Finite
State machine. Note you can formulate the State truth table
(Present State/Next State/Inputs). Please design it using D
Flip-Flops or T-Flip Flops and combination gates. Current State
Next State input Q1Q0 Q1’Q0’ D1D0 (T1T0) 00 01 01 10

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