Question

Design a 6-bit, shift-right register with D flip flops, and use it to implement a circuit that detects the sequence “010010” (the rightmost bit is the first arriving). Information shifts one position right when a positiv edge of clk occurs The circuit has the following inputs and outputs (use exactly these names for inputs and outputs. Respect upper and lower case):

• clk: Input. Clock signal.
• RST: Reset signal. When RST = 1 flip flops are reset to 0.
• IN: Data entry. IN inputs to the leftmost flip flop at each rising edge of clk.
• OUT: Output. Takes the value 1 when the last bit of sequence 010010 is detected (see example) and returns to 0 in the next clock cycle.

Note:To properly verify the circuit, VerilUOC_Desktop requires all inputs of the flip flops are connected to some value. So, it is necessary to connect "S" inputs to 0 and "load" inputs to 1. To do so, click in "Wiring" (left menu), select "Constant" and connect the constant (a logical 1) to the “load" inputs. Repeat the process and, in the Value property of the left menu, replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the "S" inputs.

Answer 1

6 bit shift register:

the positional value corresponding to 0 Q' is connected to and gate. and value position corresponding to 1 in the sequence Q is connected to and gate.

hence for 010010

we will have Q'.Q.Q'Q'Q.Q' connected to inputs of and gate respectevely.

hence giving us an output of 1. when the sequence of inputs matches the sequence.

the reset input is Asynchronous. which will reset all flip flops to 0.