Estimate tpd for a unit inverter driving m identical unit inverters.
Figure shows the equivalent circuit for the falling transition.
Each load inverter presents 3C units of gate capacitance, for a
total of 3mC. The output node also sees a capacitance of 3C from
the drain diffusions of the driving inverter. This capacitance is
called parasitic because it is an undesired side-effect of the need
to make the drain large enough to contact. The parasitic
capacitance is independent of the load that the inverter is
driving. Hence the total capacitance is (3+3m)C. The resistance is
R, so the Elmore delay is tpd= (3+3m)RC.
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