Question

1. give an instance where it would be better to infer logic rather than instantiate it.

2. give an instance where it would be better to instantiate logic rather than infer it.

(verilog)

Answer 1

Here a Verilog inference example. The synthesis tool recognizes (infers) the 8-bit up-counter with synchronous clear, and generates an appropriate register with adder logic.

Code:

module top (clk, clear, count);
  input             clk, clear;
  output reg  [7:0] count=0;

  always @ (posedge clk)
    count <= clear ? 0 : count + 1;
endmodule

If you simply drop a "COUNTER" module from your synthesis tool's library into your HDL, that's instantiation. Of course, your library may not have a COUNTER module, or it may have a different name, or it may have different I/O signals.

Code:

module top (clk, clear, count);
  input             clk, clear;
  output      [7:0] count;

  COUNTER #(.WIDTH(8)) u1 (.CLK(clk), .CLEAR(clear), .OUT(count));
endmodule

Either way, you should get very similar register/logic results in your FPGA/CPLD.