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Design the circuit of a source follower JFET amplifier biasing circuit with load RL and input...

Design the circuit of a source follower JFET amplifier biasing circuit with load RL and input voltage internal resistance RS that having a gain of +0.2. The specification of the circuit is given as below: Supply voltage, VCC = +12 V; Input impedance, Zi = 10 k; cut-off frequency from source capacitor, fLS = 40 Hz; cut-off frequency from gate capacitor, fLG = 4 Hz; VGSQ = -2.86 V; IDSS = 16 mA and Vp = -4 V

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