Question

VIVA QUESTIONS: 1. Implement the following function using VHDL coding. (Try to minimize if you can). F(A,B,C,D)=(A'+B+C). (A+B'+D'). (B+C'+D') . (A+B+C+D) 2. What will be the no. of rows in the truth table of N variables? 3. What are the advantages of VHDL? 4. Design Ex-OR gate using behavioral model? 5. Implement the following function using VHDL code f=AB+CD. 6. What are the differences between half adder and full adder? 7. What are the advantages of minimizing the logical expressions? 8. What does a combinational circuit mean? 9. Implement the half adder using VHDL code? 10. Implement the full adder using two half adders and write VHDL program in structural model?

Answer 1