the Verilog module for the dispenser is shown below
module air_freshner(clk,dispence);
input clk;// let the input clock be 10Mhz
integer count=0,count1=0;
output reg dispence;
reg s_clk=0;
always@(posedge clk)// creating a clokc of 1 sec clock period
begin
if(count == 50000000)// 10000000 for 1 sec hence for on and off we
get 1000000/2
begin
count<=0;
s_clk<=~s_clk;
end
else
count<=count+1;// counter for converting input clock to a second
time period clock
end
always@(posedge s_clk)// output block for dispencing at every
min
begin
if( count1 == 60*15 )// (60 for 1 min count for sec) and 15 for (15
minutes of each minute counted)
begin
dispence<=1;
count1<=0;
end
else
begin
dispence<=0;
count1<=count1+1;// counter for minutes
end
end
endmodule
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