Question

Design an op-amp circuit for a weighted summer that shifts the dc level of the input...

Design an op-amp circuit for a weighted summer that shifts the dc level of the input signal vi(t) = 3 sin(t) V from zero to -3 V. Assume that in addition to vi(t), you have a dc voltage source of 1.5 V available. Sketch the output signal waveform.

Homework Answers

Answer #1

The equation of summing amplifier can be write as,

Vout = Gain1 x Vin_sin + Gain2 x Vdc_1_5

Here, Vin_sin = 3sin(t) volt and Vdc_1_5 = 1.5 volt

Now, Gain1 = 1 and Gain2 = 2

Design with above can be done by,

R1 = Feedback resistor = 2 k ohm

R2 = Series resistor for 1.5 volt DC input = 1 k ohm

R3 = Series resistor for 3 volt AC input = 2 k ohm

So, Gain1 = R1/R3 = 1 and Gain2 = R1/ R2 = 2

Designed Weighted Summing Amplifier is shown below,

Input Signal Waveform,

Output Waveform,

Know the answer?
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for?
Ask your own homework help question
Similar Questions
Design an Op-Amp phase shift circuit that must accept a sine waveform voltage at its input...
Design an Op-Amp phase shift circuit that must accept a sine waveform voltage at its input ??? (?) = 10 sin (120??) mV, and must provide at its output, an output voltage of 1.2 Vrms and with an offset of −120 ° with respect to the input signal.
Design an Op-Amp Circuit that takes an input from a low current capacity voltage source (i.e....
Design an Op-Amp Circuit that takes an input from a low current capacity voltage source (i.e. a high internal impedance source) with voltage range of -15mV to 15mV, amplify it, adds a DC offset so that the voltage is always positive filter it (LPF 1, 18.3 KHz) and the convert it into digital output (reference voltage of ADC 12V). Also determine the minimum sampling rate of ADC
Using a 741 op-amp for every stage, design this circuit: The input stage has a voltage...
Using a 741 op-amp for every stage, design this circuit: The input stage has a voltage gain of 10 and input impedance of 50 K?. The low pass filter stage has a Sallen-Key (VCVS) third order butterworth response and a cutoff frequency of 5KHz. The output buffer stage has a voltage gain of 10.
Design an op-amp circuit that will provide an output voltage equal to the average of three...
Design an op-amp circuit that will provide an output voltage equal to the average of three input voltages. You may assume that the input voltages will be confined to the range -10V ?Vin ?10V. Verify your design by using Multisim software and a suitable set of input voltages.
Recommend a generalized Op Amp amplifier which processes sin wave into a cosine wave (1.5), a...
Recommend a generalized Op Amp amplifier which processes sin wave into a cosine wave (1.5), a square wave into a triangular wave (1.5), a constant DC signal into a zero-output signal (1.5) and a square wave into an impulse signal (1.5).
4. Using an op amp, design a circuit to produce an output voltage related to two...
4. Using an op amp, design a circuit to produce an output voltage related to two input voltages by the equation ?? = 1 2 ?2 − ?? (Use the feedback resistance R2 = 10kΩ). Devise a procedure to verify your design.
Design a multi-stage op-amp network that takes an input signal of vin(t) = 5 cos(120πt) V...
Design a multi-stage op-amp network that takes an input signal of vin(t) = 5 cos(120πt) V and outputs vout(t) = 2.5 + 2.5 sin(120πt) V. All resistors used must have values of at least 1 kΩ. Verify your design behaves as required using LTSpice XVII. (20 points)
Use an ideal op amp to design a differentiator circuit having a time constant of 10-5s...
Use an ideal op amp to design a differentiator circuit having a time constant of 10-5s using a 1-nF capacitor. Sketch the magnitude and phase response of the circuit, indicating the frequency at which the magnitude response equals 0 dB. A series input resistor is added to limit the gain magnitude at high frequencies to 100 V/V. Sketch the magnitude and phase responses of this modified circuit on the same axes as the ideal differentiator. How does the phase response...
1. Design a circuit with input: AC (10Vp Sin wave 50Hz), and output signal with +8.7V...
1. Design a circuit with input: AC (10Vp Sin wave 50Hz), and output signal with +8.7V and -14.7V. (Hint: Use Diodes) 2. Design an inverter circuit using PMOS. Also show the output waveform. Design on proteus.
1. Design an inverting amplifier with gain of ×10, and input impedance of 100Ω. 2. Design...
1. Design an inverting amplifier with gain of ×10, and input impedance of 100Ω. 2. Design a non-inverting amplifier with a gain of ×10. Design the amplifier so that the output current from the op-amp at maximum output voltage +15V is no larger than 15 mA. 3. Design a current summing amplifier that finds the algebraic sum of two input voltages: VOUT = - (V1 + V2) . Design the amplifier so that output current from the op-amp at maximum...