Question

Develop the VHDL Architecture for a binary up-counter that inputs a clock of 1.2 MHz and outputs a signal of 960 Hz. Use Q as the outputs and CLK as the clock input. All signals are INTEGER type.

Answer 1

The VHDL Architechture is developed by the n=10 is shown in below:-

Library IEEE;

Use IEEE . STD_LOGIC_1164 .ALL;

Use IEEE . STD_LOGIC_ARITH .ALL;

Use IEEE .STD_LOGIC_UNSIGNED . ALL;

Entity counter_VHDL is

Port (Number : in std_logic_vector(0 to 3);

Clock : in std logic;

Load: in std logic;

Reset : in std logic;

Direction: in std logic;

Output:out std_logic_vector(0 to 3));

end counter_VHDL;

architecture counter of counter_VHDL is

begin

process (CLK)

begin

if CLK event and CLK =1 then

IF Q =1249 then

Q<=0;

Else Q <= Q +1;

end IF;

end IF;

end PROCESS;

end counter;