Question

Write VHDL testbench for the next entity

Entity dec3to8 is

PORT(

AA: IN std_logic_vector(2 downto 0);

BB: OUT std_logic_vector(7 downto 0);

Enable: IN std_logic );

End entity;

Answer #1

VHDL Testbench:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity testbench is

end testbench;

architecture Behavioral of testbench is

component dec3to8 is

PORT(

AA: IN std_logic_vector(2 downto 0);

BB: OUT std_logic_vector(7 downto 0);

Enable: IN std_logic );

End component;

signal AA:std_logic_vector(2 downto 0) ;

signal BB:std_logic_vector(7 downto 0);

signal Enable : std_logic;

begin

AA<="000" , "001" after 20 ns , "010" after 40 ns , "011" after
60 ns , "100" after 80 ns , "101" after 100 ns , "110" after 120 ns
, "111" after 140 ns;

Enable<='0' , '1' after 10 ns;

uu: dec3to8 port map(AA,BB,Enable);

end Behavioral;

(Note: This testbench is written in software and it is error free.)

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