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Could someone show me how to write VHDL code for the following logical Shifts. Please use...

Could someone show me how to write VHDL code for the following logical Shifts. Please use concatenation.

signal x:std_logic_vector(7 downto 0):"01000101";

1) Logical right shift of 2.

2) Logical right shift of 5.

3) Logical left shift of 2.

3) Logical left shift of 3.

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