Question

what is the essential difference between elsif and Else if?

In VHDL

Answer 1

In VHDL every "if < condition> is followed by statement(s) which are executed in case of TRUE condition and "else" following statements are executed for FALSE condition.

Now to differentiate between elsif and else if let us take example as below:

P1: process(clk, rst)

begin

if (rst = '1') then

output <= '0';

else if rising_edge (clk) then

statement 1;

statement 2;

end if;

end if;

end process;

HERE in above process P1: statement 1 & 2 will be only executed only when rst is not 1.

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P2: process(clk, rst)

begin

if (rst = '1') then

output <= '0';

elsif rising_edge (clk) then

statement 1;

statement 2;

end if;

end if;

end process;

In the above process P2, statement 1 & 2 will get executed without checking condition of rst signal

HENCE WE CAN SAY ELSIF CLOSES THE PREVIOUS IF BLOCK AND OPENS ANOTHER IF BLOCK.

BUT ELSE IF OPENS A IF BLOCK WITHOUT CLOSING PREVIOUS IF BLOCK. ITS A NESTED IF STATEMENT type.