Q1)Design a 3-bit full adder by using a 8x3 Decoder.,
Q2)Design a digital circuit by using...
Q1)Design a 3-bit full adder by using a 8x3 Decoder.,
Q2)Design a digital circuit by using a 8x1 multiplexer
implementing the following Boolean equation.F(A, B, C, D) =∑(2, 3,
5, 7, 8, 9, 12, 13, 14, 15)
Logic Circuit
Problem #3
Given the following logic function: F(a,b,c,d) = ?
m(0,3,7,9,11,13,15)+?d(4,6,8) use a Karnaugh...
Logic Circuit
Problem #3
Given the following logic function: F(a,b,c,d) = ?
m(0,3,7,9,11,13,15)+?d(4,6,8) use a Karnaugh Map to, a) Find a
minimal SOP expression Answer: F(a,b,c,d) = b) Find a minimal POS
expression
Answer: F(a,b,c,d) =
Problem #4
Implement the function F(a,b,c,d) given in problem #3 using two
3-to-8 decoders, both active low enabled and active low output.
F(a,b,c,d) = ? m(0,3,7,9,11,13,15)+?d(4,6,8)
Answer:
Problem #5
Implement the function in the previous problem: F(a,b,c,d) = ?
m(0,3,7,9,11,13,15)+?d(4,6,8), using a single 4...
Implement F(A,B,C,D)=Σ(1,3,4,11, 13, 15) using two 3x8 AND
decoders and an enable bit.
Implement F(A,B,C,D)=Σ(1,3,4,11, 13, 15) using two 3x8 AND
decoders and an enable bit.
1) Implement the given logic function using a 4:1 MUX. (Ref: Lec
16, slide 5)
F(A,B,C)...
1) Implement the given logic function using a 4:1 MUX. (Ref: Lec
16, slide 5)
F(A,B,C) = Σm(0,1,3,7)
Show the truth table, the 4:1 MUX schematic with the inputs,
select inputs and the output.
2) For an 8:3 priority encoder:
a) Draw the schematic.
b) Write the truth table.
c) Write the Boolean expressions for each of the outputs in
terms of the inputs.
d) Draw the logic circuit for the outputs in terms of the
inputs.
1. Implement the given logic function using a 4:1 MUX. F(A,B,C)
= Σm(0,1,3,7)
Show the truth...
1. Implement the given logic function using a 4:1 MUX. F(A,B,C)
= Σm(0,1,3,7)
Show the truth table, the 4:1 MUX schematic with the inputs,
select inputs and the output.
2. For an 8:3 priority encoder:
a) Draw the schematic.
b) Write the truth table.
c) Write the Boolean expressions for each of the outputs in
terms of the inputs.
d) Draw the logic circuit for the outputs in terms of the
inputs.
(ii) Create a hierarchical Verilog 5-to-1 mux module with five
data inputs (a, b, c, d,...
(ii) Create a hierarchical Verilog 5-to-1 mux module with five
data inputs (a, b, c, d, e), three select inputs (s[2:0]), and one
output bit (f) using 4-to-1 multiplexers. Design the 4-to-1
multiplexer using behavioral code.
5 -letter "words" are formed using the letters A, B, C, D, E, F,
G. How...
5 -letter "words" are formed using the letters A, B, C, D, E, F,
G. How many such words are possible for each of the following
conditions?
a) No condition is imposed.
b) No letter can be repeated in a word.
c) Each word must begin with the letter A.
d) The letter C must be at the end.
e) The second letter must be a vowel.