Question

My question: what is the truth table for full-comparator??

Full question: Design a comparator circuit for binary numbers using only NAND gates. It should take as input two numbers represented in standard binary, X and Y, and produce two outputs, G and L, which indicate that X is Greater than or Less than Y, respectively. If both outputs are zero, it indicates that the values are equal. Design a half-comparator, full-comparator, and a full four-bit comparator. With nothing more than multiple copies of your circuit, you should be able compare numbers with an arbitrary number of bits. Turn in the truth tables, Karnaugh maps, logic expressions, and circuit diagrams for each of your individual circuits, plus a block diagram for the complete circuit. Determine the number of gate delays required by your design for a 32-bit comparator. Minimize the number of gates.

Answer #1

TRUTH TABLE FOR:

1-Bit Magnitude Comparator:

INPUT |
OUTPUT |
|||

A |
B |
A<B |
A=B |
A>B |

0 |
0 |
0 |
1 |
0 |

0 |
1 |
1 |
0 |
0 |

1 |
0 |
0 |
0 |
1 |

1 |
1 |
0 |
1 |
0 |

2-Bit Magnitude Comparator:

INPUT |
OUTPUT |
|||||

A1 |
A0 |
B1 |
B0 |
A<B |
A=B |
A>B |

0 |
0 |
0 |
0 |
0 |
1 |
0 |

0 |
0 |
0 |
1 |
1 |
0 |
0 |

0 |
0 |
1 |
0 |
1 |
0 |
0 |

0 |
0 |
1 |
1 |
1 |
0 |
0 |

0 |
1 |
0 |
0 |
0 |
0 |
1 |

0 |
1 |
0 |
1 |
0 |
1 |
0 |

0 |
1 |
1 |
0 |
1 |
0 |
0 |

0 |
1 |
1 |
1 |
1 |
0 |
0 |

1 |
0 |
0 |
0 |
0 |
0 |
1 |

1 |
0 |
0 |
1 |
0 |
0 |
1 |

1 |
0 |
1 |
0 |
0 |
1 |
0 |

1 |
0 |
1 |
1 |
1 |
0 |
0 |

1 |
1 |
0 |
0 |
0 |
0 |
1 |

1 |
1 |
0 |
1 |
0 |
0 |
1 |

1 |
1 |
1 |
0 |
0 |
0 |
1 |

1 |
1 |
1 |
1 |
0 |
1 |
0 |

I hope this will help you.

Adder
Start out by picking 2 positive six bit binary numbers that are
less than 3210, written in 2's complement notation. The
eventual goal is to add these two numbers.
1) Look at the LSB bit of the numbers, and using logic gates
(NANDs, NORs, etc.) design a circuit that correctly gives the right
output for any possible combination of bits in the LSB place.
2) Now look at the next column to the left (next to LSB). In
this...

Design a 4-bit adder-subtractor circuit using the 4-bit binary
Full adders (74LS83) and any necessary additional logic gates. The
circuit has a mode input bit, M, that controls its operation.
Specifically, when M=0, the circuit becomes a 4-bit adder, and when
M=1, the circuit becomes a 4-bit subtractor that performs the
operation A plus the 2’s complement of B.Where A and B are two
4-bits binary numbers. That is,
* When M=0, we perform A+B, and we assume that
both...

Mr Ali is undergraduate student of engineering in a University.
His registration ID is of six hexadecimal numbers (171457)16. He
needs to understand some useful operations in digital logic design
so he represented each character of his registration ID as a
four-bit number in a truth table of 16 input output relations. Then
he assigned HIGH output to each four-bit number of his registration
id and its succeeding number (all other outputs will then be
zero).
Your task is to...

Question 3 (1 point)
Which of the following reasons is why SR latches are not used to
store modern memory?
Question 3 options:
Ability to store 1 bit.
Immune to timing issues.
Ability to be implemented with gates.
Timing issues.
Question 4 (1 point)
Which of the following differentiates a latch and a flip
flop?
Question 4 options:
Usage of a clock.
Cannot toggle.
Significantly less gates needed for implementation.
Ability to store more than one bit.
Question 5 (1...

Design a counter which counts in the sequence that has
been assigned to you. Use D flip flops and NAND gates. Simulate
your design using SimUaid.
Submit the state table, D flip-flop input equations,
and transition graph determined in Part 6. The D flip-flop
equations can be derived using Karnaugh maps or using LogicAid by
entering a state table with zero input variables.
Sequence: 000,100,001,110,101,111,(repeat)
000,...
Also, please answer the following questions:
How can a D flip-flop be set to...

Question 4. [20 marks] A jet aircraft employs a system for
monitoring the speed S , pressure P , and temperature T
values of its engines using sensors that operate as follows:
S sensor output = 0 only when T SS (rpm) P sensor output = 0 only
when T PP (psi) T sensor output = 0 only when T TT (℉). Assume
that a HIGH at output W activates the...

The questions:
1. What type of technology Acme and Omega utilize to transform
inputs into outputs?
2. Which strategic choice (differentiation or cost leadership)
suits best to Acme? Omega? Do these companies have clear strategic
choices or do they stuck in the middle?
3. Based on all the contingencies which type of structure is
more suitable for these companies; mechanistic or organic?
please answer each question alone
The Paradoxical Twins: Acme and Omega Electronics John F. Veiga
Part! boom of...

What tools could AA leaders have used to increase their
awareness of internal and external issues?
???ALASKA AIRLINES: NAVIGATING CHANGE
In the autumn of 2007, Alaska Airlines executives adjourned at
the end of a long and stressful day in the
midst of a multi-day strategic planning session. Most headed
outside to relax, unwind and enjoy a bonfire
on the shore of Semiahmoo Spit, outside the meeting venue in
Blaine, a seaport town in northwest
Washington state.
Meanwhile, several members of...

ADVERTISEMENT

Get Answers For Free

Most questions answered within 1 hours.

ADVERTISEMENT

asked 22 minutes ago

asked 40 minutes ago

asked 43 minutes ago

asked 45 minutes ago

asked 58 minutes ago

asked 1 hour ago

asked 1 hour ago

asked 1 hour ago

asked 1 hour ago

asked 1 hour ago

asked 1 hour ago

asked 1 hour ago