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What modification should be made in MIPS data-path architecture to support pipelining and how many clock...

What modification should be made in MIPS data-path architecture to support pipelining and how many clock cycles should the pipeline stall when forwarding is unable to solve the data hazard?

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We need to add or modify the State registers between in each pipeline stage to isolate them in MIPS data-path architecture.

when the forwarding is unable to solve the data hazard three clock cycle should the pipeline stall.

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