Question

Consider the amplifier circuit of Fig. 5.39(a) without the load resistance and with channel length modulation neglected. Let V, V, and mA/V2 . Find , , and to obtain a voltage gain of 25 V/V and an input resistance of 0.5 M . What is the maximum allowable input signal, ?

Answer #1

Design the circuit of a source follower JFET amplifier biasing
circuit with load RL and input voltage internal resistance RS that
having a gain of +0.2. The specification of the circuit is given as
below: Supply voltage, VCC = +12 V; Input impedance, Zi = 10 k;
cut-off frequency from source capacitor, fLS = 40 Hz; cut-off
frequency from gate capacitor, fLG = 4 Hz; VGSQ = -2.86 V; IDSS =
16 mA and Vp = -4 V

In a two-story voltage amplifier circuit, there is PNP on the
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and a total of 5 capacitors were used in the circuit, 5 resistors
per floor. Re resistance of PNP transistor is 63.31 Ω and re
resistance of NPN transistor is 15.25 Ω. The input impedance of the
first floor is 212.36 Ω and the input impedance of the second floor
is 9.1 K Ω. There is...

Design, simulate, and implement a multistage discrete amplifier
using small-signal BJT transistors.
Amplifier Specifications:
– Midband voltage gain: Av = 100.
– Lower 3-dB frequency: fc = 100 Hz.
– Input Impedance: Zin ≥ 250 kΩ.
– Output Impedance: Zo ≤ 100 Ω.
– Power Supply: Vcc = 15 V.
– The load resistance is 1 kΩ
– Output capability with a 1–kHz sinusoidal test signal must be
at least 2 V peak without severe distortion (i.e. clipping).
– Transistor...

Consider an op-amp connected in an inverting configuration to
realize a closed-loop gain of -100 V/V utilizing resistors of 1k
and 100 k. A load resistance RLis connected from the output to
ground, and a low-frequency sine-wave signal of peak amplitude
Vpeakis applied to the input. Let the op amp be ideal except that
its output voltage saturates at 10 Vand its output current is
limited to the range of 20 mA.
1) For RL = 1k, what is the...

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