Question

Consider the following instruction:

OR Rd, Rs, Rt

Which has the following meaning in Verilog: Reg[Rd] = Reg[Rs] OR Reg[Rt]

Fill out the table below to show what values the control block provides to each output it is connected to:

RegWrite	MemRead	ALUMux	MemWrite	ALUop	RegMux	Branch
				OR

Answer 1

Here is the complete answer to the given question along with an explanation for the same:

RegWrite -> 1 (Since the OR instructions writes into the register Rd)

MemRead -> x (don't care, Since Memory may or may not be read)

ALUMux -> 0 (Since the value output from the register file is passed to the ALU)

MemWrite -> 0 (Since the memory is not to be written into)

ALUop -> 1x (since the operation is OR)

RegMux -> 1 (Since Rd is the register to be written)

Branch -> 0 (The instruction is no a branch instruction)

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