Question

Recall that performing a read from a dynamic RAM (DRAM) requires that the chip precharge before it can supply the requested data. Assume that the precharge takes 10ns and it takes 15ns to output the requested data in response to a read operation or to store the input data for a write operation. Also recall that our MIPS pipeline system employs a Harvard Architecture, transfers 32 bits at a time between the CPU and memory, and each pipeline stage consumes one clock cycle.

1. What is the maximum clock rate (expressed in GHz) that can be used for our 5-stage pipelined system if this type of DRAM is used for the memory?                
2. If the instruction memory is implemented as a single memory module with a storage capacity of 256 * 2²⁰ bytes, what is its width and its depth?

Answer 1