Question

T1 : IR <- M[AR]

Assuming that one clock is needed to retrieve data from memory.

If you need two blocks to read from memory,

How should the Fetch & Decode part change?

Answer 1

Fatch phase

   

// starting address present in program counter(PC) at the time when program is loaded in main memory. Load value present in Program counter in Address Registor(AR).

// Retrieve the data from memory and increment the program counter.

Decode phase

// decode the 12th,13th,14th bits of IR using 3x8 Decoder and get decode output as ( D7,D6,D5,D4,D3,D2,D1,D0 ).

// Load the operand part value of IR (i.e., 11,10,9,......,1,0th bits) in AR.

Assuming that Instruction register(IR) is 16 bit.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
I	3x8 Decoder	operands

This Instruction cycle is execute only one instruction.

For two blocks of instruction to execute, we have to process this cycle number of times.