Question

What is the actual memory size for the following cache configurations? You need to calculate the...

What is the actual memory size for the following cache configurations? You need to calculate the overhead (tag plus valid bit). Assume 32-bit memory address
a. 128 KB cache with 8-byte block, direct-mapped
b. 128 KB cache with 8-byte block, 8-way set associative
c. 128 KB cache with 16-byte block, direct-mapped
d. 128 KB cache wit 16-byte block, 8-way set associative

Homework Answers

Know the answer?
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for?
Ask your own homework help question
Similar Questions
Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a...
Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a cache of 128 blocks, where each cache block contains 8 bytes. For four-way set associative cache, to which block of cache the address 0x1895BA maps? Group of answer choices Block 70 Block 16 Block 23 Not enough information
A 16 GB main memory has a 8 MB cache organized as a 8-way set associative...
A 16 GB main memory has a 8 MB cache organized as a 8-way set associative cache with 128 Byte cache blocks (line). How many cache blocks are there in the cache? How many sets are there in the cache? (Show your computation.) Show how the 36-bit address generated by the CPU would be divided to map into the cache. (Indicate the sizes of the tag, line, etc.)
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 1) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 2) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
1. Suppose we have a 32KB direct-mapped data cache with 32-byte blocks. a) Show how a...
1. Suppose we have a 32KB direct-mapped data cache with 32-byte blocks. a) Show how a 32-bit memory address is divided into tag, index and offset. Show clearly how many bits are in each field. b) How many total bits are there in this cache? 2. Suppose we have a 8KB direct-mapped data cache with 64-byte blocks. a) Show how a 32-bit memory address is divided into tag, index and offset. Show clearly how many bits are in each field....
14. For a direct-mapped cache with a 32-bit address and 32-bit words, the following address bits...
14. For a direct-mapped cache with a 32-bit address and 32-bit words, the following address bits are used to access the cache. Tag Index Offset 31-16 15-5 4-0 What is the cache block size (in words)? How many blocks does the cache have?
Assume a byte-addressable memory has 64K bytes. Blocks are 8 bytes in length and the cache...
Assume a byte-addressable memory has 64K bytes. Blocks are 8 bytes in length and the cache consists of 4K bytes. Show the format for a main memory address assuming a 4-way set associative cache mapping scheme. Include the field names as well as their sizes. A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main...
Assuming that a computer system has 64MBytes of main memory, 16Bytes of cache line and 64KBytes...
Assuming that a computer system has 64MBytes of main memory, 16Bytes of cache line and 64KBytes of cache size. A main memory address contains “A1E3”data in a particular memory cell. Transfer this data to the cache in direct mapping, associative mapping and 16-way set-associative mapping algorithms.
Assume a byte-addressable memory consisting of 1G (230) bytes. A Direct Mapped Cache contains 256 (28)...
Assume a byte-addressable memory consisting of 1G (230) bytes. A Direct Mapped Cache contains 256 (28) blocks of 2048 (211) bytes each. Therefore the 30 bits address is partitioned into three areas of the following sizes (in bits): offset bits block bits tag bits
Consider a cache of 4 lines of 16 bytes each. Main memory is divided into blocks...
Consider a cache of 4 lines of 16 bytes each. Main memory is divided into blocks of 16 bytes each. That is, block 0 has bytes with addresses 0 through 15, and so on. Now consider a program that accesses memory in the following sequence of addresses: Once: 63 through 70. Loop two times: 15 through 32; 80 through 95. Suppose the cache is organized as two-​way set associative, with two sets of two lines each. Even-​numbered blocks are assigned...
ADVERTISEMENT
Need Online Homework Help?

Get Answers For Free
Most questions answered within 1 hours.

Ask a Question
ADVERTISEMENT