Question

Use OR gate(s), AND gate(s) and XOR gate(s) to design a 1-bit full adder. The number of gates should be minimized by using De Morgan’s law. Your solution should be different from the design I showed you in the class. Please show the process of getting to the solution in your report and draw the circuit by using MMLogic. Submit your report together with the MMLogic file.

Answer 1

Solution:

Solution for the problem is provided below, please comment if any doubts:

The truth table of the 1 bit adder can be implemented as given below:

A	B	Cin	S	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Implement the K-map to reduce the relation for S and Cout.