Question

Consider a virtual memory system that can address a total of 232 bytes. You have unlimited...

  1. Consider a virtual memory system that can address a total of 232 bytes. You have unlimited hard drive space, but are limited to only 8 MB of physical memory. Assume that virtual and physical pages are each 4 KB in size. a. How many bits is the physical address?
    1. What is the maximum number of virtual pages in the system?
    2. How many physical pages are in the system?
    3. How many bits are the virtual and physical page numbers?
    4. Suppose that you come up with a direct mapped scheme that maps virtual pages to physical pages. The mapping uses the least significant bits of the virtual page number to determine the physical page number. How many virtual pages are mapped to each physical page? Why is this “direct mapping” a bad plan?
    5. Clearly, a more flexible and dynamic scheme for translating virtual addresses into physical addresses is required than the one described in part (e). Suppose you use a page table to store mappings (translations from virtual page number to physical page number). How many page table entries will the page table contain?
    6. Assume that, in addition to the physical page number, each page table entry also contains some status information in the form of a valid bit (V) and a dirty bit (D). How many bytes long is each page table entry?

(Round up to an integer number of bytes.)

  1. Sketch the layout of the page table. What is the total size of the page table in bytes?

Homework Answers

Know the answer?
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for?
Ask your own homework help question
Similar Questions
Consider a process with a logical address space of 4 pages of 1024 bytes per page,...
Consider a process with a logical address space of 4 pages of 1024 bytes per page, mapped onto a physical memory of 64 frames. A. How many bits are there in the logical address? B. How many bits are there in the physical address? C. Given the following page table map: page 0 is mapped to frame 3, page 1 is mapped to frame 14, page 2 to frame 6, and page 3 to frame 33, what is the physical...
A mobile device has 4 GB of main memory and 128 GB of secondary storage. The...
A mobile device has 4 GB of main memory and 128 GB of secondary storage. The page size is 4 KB. Each page table entry is 8 bytes. Compute the following values: # bits in virtual address: # bits in physical address: total # of possible pages in virtual address space: # pages for the page table:
1a) A memory unit has 28-bit address lines and 64-bit input/output data lines. How many bytes...
1a) A memory unit has 28-bit address lines and 64-bit input/output data lines. How many bytes of data can this memory hold? How many words does it contain, and how large is each word? b) A memory unit consists of 32M words of 16-bit each. How many bits wide address lines and input-output data lines are needed to access this memory? c) A memory unit consists of 512K bytes of data. How many bits wide address lines are needed to...
The following is a page table for a system with 12-bit virtual and physical addresses and...
The following is a page table for a system with 12-bit virtual and physical addresses and 256-byte pages. Free page frames are to be allocated in the order 9, 15, 5. A dash for a page frame indicates that the pagesis not in memory. Page Page Frame 0 4 1 11 2 10 3 - 4 - 5 2 6 - 7 0 8 12 9 1 Convert the following virtual addresses (given in hexadecimal) to their equivalent physical. Assume...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 1) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 2) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
Assume a byte-addressable memory has 64K bytes. Blocks are 8 bytes in length and the cache...
Assume a byte-addressable memory has 64K bytes. Blocks are 8 bytes in length and the cache consists of 4K bytes. Show the format for a main memory address assuming a 4-way set associative cache mapping scheme. Include the field names as well as their sizes. A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main...
1. The TLB holds Question 1 options: L1 Cache address Virtual memory address Data Location of...
1. The TLB holds Question 1 options: L1 Cache address Virtual memory address Data Location of logical addresses Question 2 (1 point) Content addressable memory Question 2 options: Is used in cache memory. Is broken into multiple sections. Is used in binary files. Is used in standard program execution. Question 3 (1 point) Thrashing is caused by Question 3 options: The usage of segmentation in memory organization. The usage of paging in memory organization. Pages being swapped back and forth...
1. The memory units that follow are specified by the number of words times the number...
1. The memory units that follow are specified by the number of words times the number of bits per word. How many address lines and input/output data lines are needed in each case? (a) 8K X 16 (b) 2G X 8 (c) 16M X 32 (d) 256K X 64 2. Give the number of bytes stored in each memory unit in question 1. 3. Word number 563 decimal in the memory shown in Fig. 7.3 (see Mano-Ch7.pdf) contains the binary...
A digital computer has a memory unit with 32 bits per word. The instruction set consists...
A digital computer has a memory unit with 32 bits per word. The instruction set consists of 147 different operations. All instructions have an operation code part (opcode) and two address fields: one for a memory address and one for a register address. This particular system includes eight general-purpose, user-addressable registers. Registers may be loaded directly from memory, and memory may be updated directly from the registers. Direct memory-to-memory data movement operations are not supported. Each instruction stored in one...
ADVERTISEMENT
Need Online Homework Help?

Get Answers For Free
Most questions answered within 1 hours.

Ask a Question
ADVERTISEMENT